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61 lines
2.7 KiB
Diff
61 lines
2.7 KiB
Diff
commit eb92f5a745014532b83abfba04602fce87ca8393
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Author: Chuang-Yu Cheng <cycheng@multicorewareinc.com>
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Date: Fri Apr 8 12:04:32 2016 +0000
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CXX_FAST_TLS calling convention: performance improvement for PPC64
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This is the same change on PPC64 as r255821 on AArch64. I have even borrowed
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his commit message.
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The access function has a short entry and a short exit, the initialization
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block is only run the first time. To improve the performance, we want to
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have a short frame at the entry and exit.
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We explicitly handle most of the CSRs via copies. Only the CSRs that are not
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handled via copies will be in CSR_SaveList.
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Frame lowering and prologue/epilogue insertion will generate a short frame
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in the entry and exit according to CSR_SaveList. The majority of the CSRs will
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be handled by register allcoator. Register allocator will try to spill and
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reload them in the initialization block.
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We add CSRsViaCopy, it will be explicitly handled during lowering.
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1> we first set FunctionLoweringInfo->SplitCSR if conditions are met (the target
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supports it for the given machine function and the function has only return
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exits). We also call TLI->initializeSplitCSR to perform initialization.
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2> we call TLI->insertCopiesSplitCSR to insert copies from CSRsViaCopy to
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virtual registers at beginning of the entry block and copies from virtual
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registers to CSRsViaCopy at beginning of the exit blocks.
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3> we also need to make sure the explicit copies will not be eliminated.
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Author: Tom Jablin (tjablin)
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Reviewers: hfinkel kbarton cycheng
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http://reviews.llvm.org/D17533
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265781 91177308-0d34-0410-b5e6-96231b3b80d8
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diff --git a/lib/CodeGen/TargetFrameLoweringImpl.cpp b/lib/CodeGen/TargetFrameLoweringImpl.cpp
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index 679ade1..0a0e079 100644
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--- a/lib/CodeGen/TargetFrameLoweringImpl.cpp
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+++ b/lib/CodeGen/TargetFrameLoweringImpl.cpp
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@@ -63,12 +63,15 @@ void TargetFrameLowering::determineCalleeSaves(MachineFunction &MF,
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const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
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const MCPhysReg *CSRegs = TRI.getCalleeSavedRegs(&MF);
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+ // Resize before the early returns. Some backends expect that
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+ // SavedRegs.size() == TRI.getNumRegs() after this call even if there are no
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+ // saved registers.
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+ SavedRegs.resize(TRI.getNumRegs());
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+
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// Early exit if there are no callee saved registers.
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if (!CSRegs || CSRegs[0] == 0)
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return;
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- SavedRegs.resize(TRI.getNumRegs());
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-
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// In Naked functions we aren't going to save any registers.
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if (MF.getFunction()->hasFnAttribute(Attribute::Naked))
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return;
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