forked from mirrors/nixpkgs
3874e5812d
(less sigill, less sigbus). Related to bad handling of FPU instructions. I apply them only to linux 3.4, although I think they can apply to many older kernels too. svn path=/nixpkgs/trunk/; revision=34522
145 lines
4 KiB
Diff
145 lines
4 KiB
Diff
From ab1ce0a6cd51ca83194a865837f3b90f366a733d Mon Sep 17 00:00:00 2001
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From: Lluis Batlle i Rossell <viric@viric.name>
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Date: Sat, 16 Jun 2012 00:22:53 +0200
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Subject: [PATCH] MIPS: Add emulation for fpureg-mem unaligned access
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To: linux-mips@linux-mips.org
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Cc: loongson-dev@googlegroups.com
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Reusing most of the code from lw,ld,sw,sd emulation,
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I add the emulation for lwc1,ldc1,swc1,sdc1.
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This avoids the direct SIGBUS sent to userspace processes that have
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misaligned memory accesses.
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I've tested the change in Loongson2F, with an own test program, and
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WebKit 1.4.0, as both were killed by sigbus without this patch.
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Signed-off: Lluis Batlle i Rossell <viric@viric.name>
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---
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arch/mips/kernel/unaligned.c | 43 +++++++++++++++++++++++++++++-------------
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1 file changed, 30 insertions(+), 13 deletions(-)
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diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
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index 9c58bdf..4531e6c 100644
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--- a/arch/mips/kernel/unaligned.c
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+++ b/arch/mips/kernel/unaligned.c
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@@ -85,6 +85,7 @@
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#include <asm/cop2.h>
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#include <asm/inst.h>
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#include <asm/uaccess.h>
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+#include <asm/fpu.h>
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#define STR(x) __STR(x)
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#define __STR(x) #x
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@@ -108,6 +109,7 @@ static void emulate_load_store_insn(struct pt_regs *regs,
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union mips_instruction insn;
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unsigned long value;
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unsigned int res;
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+ fpureg_t *fpuregs;
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perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
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@@ -183,6 +185,7 @@ static void emulate_load_store_insn(struct pt_regs *regs,
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break;
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case lw_op:
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+ case lwc1_op:
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if (!access_ok(VERIFY_READ, addr, 4))
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goto sigbus;
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@@ -209,7 +212,12 @@ static void emulate_load_store_insn(struct pt_regs *regs,
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if (res)
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goto fault;
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compute_return_epc(regs);
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- regs->regs[insn.i_format.rt] = value;
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+ if (insn.i_format.opcode == lw_op) {
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+ regs->regs[insn.i_format.rt] = value;
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+ } else {
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+ fpuregs = get_fpu_regs(current);
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+ fpuregs[insn.i_format.rt] = value;
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+ }
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break;
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case lhu_op:
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@@ -291,6 +299,7 @@ static void emulate_load_store_insn(struct pt_regs *regs,
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goto sigill;
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case ld_op:
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+ case ldc1_op:
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#ifdef CONFIG_64BIT
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/*
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* A 32-bit kernel might be running on a 64-bit processor. But
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@@ -325,7 +334,12 @@ static void emulate_load_store_insn(struct pt_regs *regs,
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if (res)
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goto fault;
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compute_return_epc(regs);
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- regs->regs[insn.i_format.rt] = value;
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+ if (insn.i_format.opcode == ld_op) {
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+ regs->regs[insn.i_format.rt] = value;
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+ } else {
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+ fpuregs = get_fpu_regs(current);
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+ fpuregs[insn.i_format.rt] = value;
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+ }
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break;
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#endif /* CONFIG_64BIT */
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@@ -370,10 +384,16 @@ static void emulate_load_store_insn(struct pt_regs *regs,
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break;
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case sw_op:
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+ case swc1_op:
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if (!access_ok(VERIFY_WRITE, addr, 4))
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goto sigbus;
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- value = regs->regs[insn.i_format.rt];
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+ if (insn.i_format.opcode == sw_op) {
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+ value = regs->regs[insn.i_format.rt];
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+ } else {
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+ fpuregs = get_fpu_regs(current);
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+ value = fpuregs[insn.i_format.rt];
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+ }
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__asm__ __volatile__ (
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#ifdef __BIG_ENDIAN
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"1:\tswl\t%1,(%2)\n"
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@@ -401,6 +421,7 @@ static void emulate_load_store_insn(struct pt_regs *regs,
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break;
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case sd_op:
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+ case sdc1_op:
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#ifdef CONFIG_64BIT
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/*
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* A 32-bit kernel might be running on a 64-bit processor. But
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@@ -412,7 +433,12 @@ static void emulate_load_store_insn(struct pt_regs *regs,
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if (!access_ok(VERIFY_WRITE, addr, 8))
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goto sigbus;
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- value = regs->regs[insn.i_format.rt];
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+ if (insn.i_format.opcode == sd_op) {
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+ value = regs->regs[insn.i_format.rt];
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+ } else {
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+ fpuregs = get_fpu_regs(current);
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+ value = fpuregs[insn.i_format.rt];
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+ }
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__asm__ __volatile__ (
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#ifdef __BIG_ENDIAN
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"1:\tsdl\t%1,(%2)\n"
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@@ -443,15 +469,6 @@ static void emulate_load_store_insn(struct pt_regs *regs,
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/* Cannot handle 64-bit instructions in 32-bit kernel */
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goto sigill;
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- case lwc1_op:
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- case ldc1_op:
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- case swc1_op:
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- case sdc1_op:
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- /*
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- * I herewith declare: this does not happen. So send SIGBUS.
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- */
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- goto sigbus;
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-
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/*
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* COP2 is available to implementor for application specific use.
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* It's up to applications to register a notifier chain and do
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--
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1.7.9.5
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