forked from mirrors/nixpkgs
Adding two kernel patches for mips, that make the life easier on loongson2f
(less sigill, less sigbus). Related to bad handling of FPU instructions. I apply them only to linux 3.4, although I think they can apply to many older kernels too. svn path=/nixpkgs/trunk/; revision=34522
This commit is contained in:
Lluís Batlle i Rossell
parent
404c21de2f
commit
3874e5812d
108
pkgs/os-specific/linux/kernel/mips-fpu-sigill.patch
Normal file
108
pkgs/os-specific/linux/kernel/mips-fpu-sigill.patch
Normal file
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@ -0,0 +1,108 @@
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From bf55ef4e3c2f622ac013f196affbd11b67b59223 Mon Sep 17 00:00:00 2001
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From: Mark H Weaver <mhw@netris.org>
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Date: Fri, 28 Oct 2011 13:24:37 -0400
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Subject: [PATCH 2/4] Fix handling of prefx instruction in mips/math-emu
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* The instruction is named prefx, not pfetch, and its function
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field is 0x17, not 0x07.
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* Recognize the prefx instruction regardless of what bits happen to be
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in bits 21-25, which is the format field of the floating-point ops,
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but holds the base register of the prefx instruction.
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---
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arch/mips/include/asm/inst.h | 4 ++--
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arch/mips/math-emu/cp1emu.c | 16 +++++++---------
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2 files changed, 9 insertions(+), 11 deletions(-)
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diff --git a/arch/mips/include/asm/inst.h b/arch/mips/include/asm/inst.h
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index ab84064..3048edc 100644
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--- a/arch/mips/include/asm/inst.h
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+++ b/arch/mips/include/asm/inst.h
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@@ -161,8 +161,8 @@ enum cop1_sdw_func {
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*/
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enum cop1x_func {
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lwxc1_op = 0x00, ldxc1_op = 0x01,
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- pfetch_op = 0x07, swxc1_op = 0x08,
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- sdxc1_op = 0x09, madd_s_op = 0x20,
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+ swxc1_op = 0x08, sdxc1_op = 0x09,
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+ prefx_op = 0x17, madd_s_op = 0x20,
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madd_d_op = 0x21, madd_e_op = 0x22,
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msub_s_op = 0x28, msub_d_op = 0x29,
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msub_e_op = 0x2a, nmadd_s_op = 0x30,
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diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
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index dbf2f93..87ddba1 100644
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--- a/arch/mips/math-emu/cp1emu.c
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+++ b/arch/mips/math-emu/cp1emu.c
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@@ -739,7 +739,7 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
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break;
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default:
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- return SIGILL;
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+ goto SIGILL_unless_prefx_op;
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}
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break;
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}
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@@ -809,19 +809,17 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
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goto copcsr;
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default:
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- return SIGILL;
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+ goto SIGILL_unless_prefx_op;
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}
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break;
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}
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- case 0x7: /* 7 */
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- if (MIPSInst_FUNC(ir) != pfetch_op) {
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- return SIGILL;
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- }
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- /* ignore prefx operation */
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- break;
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-
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default:
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+ SIGILL_unless_prefx_op:
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+ if (MIPSInst_FUNC(ir) == prefx_op) {
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+ /* ignore prefx operation */
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+ break;
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+ }
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return SIGILL;
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}
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--
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1.7.5.4
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From 97a564e3eddbfb84844b8eccb3bd751c71dfb3eb Mon Sep 17 00:00:00 2001
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From: Mark H Weaver <mhw@netris.org>
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Date: Fri, 28 Oct 2011 13:35:27 -0400
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Subject: [PATCH 3/4] Don't process empty cause flags after simple fp move on
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mips
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---
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arch/mips/math-emu/cp1emu.c | 4 ++--
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1 files changed, 2 insertions(+), 2 deletions(-)
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diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
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index 87ddba1..fefcba2 100644
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--- a/arch/mips/math-emu/cp1emu.c
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+++ b/arch/mips/math-emu/cp1emu.c
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@@ -912,7 +912,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
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case fmov_op:
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/* an easy one */
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SPFROMREG(rv.s, MIPSInst_FS(ir));
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- goto copcsr;
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+ break;
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/* binary op on handler */
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scopbop:
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@@ -1099,7 +1099,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
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case fmov_op:
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/* an easy one */
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DPFROMREG(rv.d, MIPSInst_FS(ir));
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- goto copcsr;
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+ break;
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/* binary op on handler */
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dcopbop:{
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--
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1.7.5.4
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144
pkgs/os-specific/linux/kernel/mips-fpureg-emulation.patch
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144
pkgs/os-specific/linux/kernel/mips-fpureg-emulation.patch
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@ -0,0 +1,144 @@
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From ab1ce0a6cd51ca83194a865837f3b90f366a733d Mon Sep 17 00:00:00 2001
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From: Lluis Batlle i Rossell <viric@viric.name>
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Date: Sat, 16 Jun 2012 00:22:53 +0200
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Subject: [PATCH] MIPS: Add emulation for fpureg-mem unaligned access
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To: linux-mips@linux-mips.org
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Cc: loongson-dev@googlegroups.com
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Reusing most of the code from lw,ld,sw,sd emulation,
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I add the emulation for lwc1,ldc1,swc1,sdc1.
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This avoids the direct SIGBUS sent to userspace processes that have
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misaligned memory accesses.
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I've tested the change in Loongson2F, with an own test program, and
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WebKit 1.4.0, as both were killed by sigbus without this patch.
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Signed-off: Lluis Batlle i Rossell <viric@viric.name>
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---
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arch/mips/kernel/unaligned.c | 43 +++++++++++++++++++++++++++++-------------
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1 file changed, 30 insertions(+), 13 deletions(-)
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diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
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index 9c58bdf..4531e6c 100644
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--- a/arch/mips/kernel/unaligned.c
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+++ b/arch/mips/kernel/unaligned.c
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@@ -85,6 +85,7 @@
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#include <asm/cop2.h>
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#include <asm/inst.h>
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#include <asm/uaccess.h>
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+#include <asm/fpu.h>
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#define STR(x) __STR(x)
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#define __STR(x) #x
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@@ -108,6 +109,7 @@ static void emulate_load_store_insn(struct pt_regs *regs,
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union mips_instruction insn;
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unsigned long value;
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unsigned int res;
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+ fpureg_t *fpuregs;
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perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
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@@ -183,6 +185,7 @@ static void emulate_load_store_insn(struct pt_regs *regs,
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break;
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case lw_op:
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+ case lwc1_op:
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if (!access_ok(VERIFY_READ, addr, 4))
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goto sigbus;
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@@ -209,7 +212,12 @@ static void emulate_load_store_insn(struct pt_regs *regs,
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if (res)
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goto fault;
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compute_return_epc(regs);
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- regs->regs[insn.i_format.rt] = value;
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+ if (insn.i_format.opcode == lw_op) {
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+ regs->regs[insn.i_format.rt] = value;
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+ } else {
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+ fpuregs = get_fpu_regs(current);
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+ fpuregs[insn.i_format.rt] = value;
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+ }
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break;
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case lhu_op:
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@@ -291,6 +299,7 @@ static void emulate_load_store_insn(struct pt_regs *regs,
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goto sigill;
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case ld_op:
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+ case ldc1_op:
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#ifdef CONFIG_64BIT
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/*
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* A 32-bit kernel might be running on a 64-bit processor. But
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@@ -325,7 +334,12 @@ static void emulate_load_store_insn(struct pt_regs *regs,
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if (res)
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goto fault;
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compute_return_epc(regs);
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- regs->regs[insn.i_format.rt] = value;
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+ if (insn.i_format.opcode == ld_op) {
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+ regs->regs[insn.i_format.rt] = value;
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+ } else {
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+ fpuregs = get_fpu_regs(current);
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+ fpuregs[insn.i_format.rt] = value;
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+ }
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break;
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#endif /* CONFIG_64BIT */
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@@ -370,10 +384,16 @@ static void emulate_load_store_insn(struct pt_regs *regs,
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break;
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case sw_op:
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+ case swc1_op:
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if (!access_ok(VERIFY_WRITE, addr, 4))
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goto sigbus;
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- value = regs->regs[insn.i_format.rt];
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+ if (insn.i_format.opcode == sw_op) {
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+ value = regs->regs[insn.i_format.rt];
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+ } else {
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+ fpuregs = get_fpu_regs(current);
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+ value = fpuregs[insn.i_format.rt];
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+ }
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__asm__ __volatile__ (
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#ifdef __BIG_ENDIAN
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"1:\tswl\t%1,(%2)\n"
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@@ -401,6 +421,7 @@ static void emulate_load_store_insn(struct pt_regs *regs,
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break;
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case sd_op:
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+ case sdc1_op:
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#ifdef CONFIG_64BIT
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/*
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* A 32-bit kernel might be running on a 64-bit processor. But
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@@ -412,7 +433,12 @@ static void emulate_load_store_insn(struct pt_regs *regs,
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if (!access_ok(VERIFY_WRITE, addr, 8))
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goto sigbus;
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- value = regs->regs[insn.i_format.rt];
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+ if (insn.i_format.opcode == sd_op) {
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+ value = regs->regs[insn.i_format.rt];
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+ } else {
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+ fpuregs = get_fpu_regs(current);
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+ value = fpuregs[insn.i_format.rt];
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+ }
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__asm__ __volatile__ (
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#ifdef __BIG_ENDIAN
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"1:\tsdl\t%1,(%2)\n"
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@@ -443,15 +469,6 @@ static void emulate_load_store_insn(struct pt_regs *regs,
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/* Cannot handle 64-bit instructions in 32-bit kernel */
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goto sigill;
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- case lwc1_op:
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- case ldc1_op:
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- case swc1_op:
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- case sdc1_op:
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- /*
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- * I herewith declare: this does not happen. So send SIGBUS.
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- */
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- goto sigbus;
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-
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/*
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* COP2 is available to implementor for application specific use.
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* It's up to applications to register a notifier chain and do
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--
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1.7.9.5
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@ -353,6 +353,16 @@ rec {
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patch = ./mips_restart.patch;
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};
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mips_fpureg_emu =
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{ name = "mips-fpureg-emulation";
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patch = ./mips-fpureg-emulation.patch;
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};
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mips_fpu_sigill =
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{ name = "mips-fpu-sigill";
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patch = ./mips-fpu-sigill.patch;
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};
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guruplug_defconfig =
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{ # Default configuration for the GuruPlug. From
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# <http://www.openplug.org/plugwiki/images/c/c6/Guruplug-patchset-2.6.33.2.tar.bz2>.
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@ -5681,6 +5681,9 @@ let
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[ #kernelPatches.fbcondecor_2_6_38
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kernelPatches.sec_perm_2_6_24
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kernelPatches.aufs3_4
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] ++ lib.optionals (platform.kernelArch == "mips")
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[ kernelPatches.mips_fpureg_emu
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kernelPatches.mips_fpu_sigill
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];
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};
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