From 123ec3463804e23962b2fe36ea3041648b48fb71 Mon Sep 17 00:00:00 2001 From: "Markus S. Wamser" Date: Thu, 22 Oct 2020 01:04:26 +0200 Subject: [PATCH] ghdl: fix llvm backend, add passthru.tests --- pkgs/development/compilers/ghdl/default.nix | 12 ++- .../compilers/ghdl/expected-output.txt | 8 ++ pkgs/development/compilers/ghdl/simple-tb.vhd | 78 +++++++++++++++++++ pkgs/development/compilers/ghdl/simple.vhd | 45 +++++++++++ .../compilers/ghdl/test-simple.nix | 23 ++++++ 5 files changed, 165 insertions(+), 1 deletion(-) create mode 100644 pkgs/development/compilers/ghdl/expected-output.txt create mode 100644 pkgs/development/compilers/ghdl/simple-tb.vhd create mode 100644 pkgs/development/compilers/ghdl/simple.vhd create mode 100644 pkgs/development/compilers/ghdl/test-simple.nix diff --git a/pkgs/development/compilers/ghdl/default.nix b/pkgs/development/compilers/ghdl/default.nix index e73324394394..ec07331dc52b 100644 --- a/pkgs/development/compilers/ghdl/default.nix +++ b/pkgs/development/compilers/ghdl/default.nix @@ -1,4 +1,4 @@ -{ stdenv, fetchFromGitHub, gnat, zlib, llvm, lib +{ stdenv, fetchFromGitHub, callPackage, gnat, zlib, llvm, lib , backend ? "mcode" }: assert backend == "mcode" || backend == "llvm"; @@ -17,6 +17,7 @@ stdenv.mkDerivation rec { LIBRARY_PATH = "${stdenv.cc.libc}/lib"; buildInputs = [ gnat zlib ] ++ lib.optional (backend == "llvm") [ llvm ]; + propagatedBuildInputs = lib.optionals (backend == "llvm") [ zlib ]; preConfigure = '' # If llvm 7.0 works, 7.x releases should work too. @@ -30,6 +31,15 @@ stdenv.mkDerivation rec { enableParallelBuilding = true; + passthru = { + # run with either of + # nix-build -A ghdl-mcode.passthru.tests + # nix-build -A ghdl-llvm.passthru.tests + tests = { + simple = callPackage ./test-simple.nix { inherit backend; }; + }; + }; + meta = with lib; { homepage = "https://github.com/ghdl/ghdl"; description = "VHDL 2008/93/87 simulator"; diff --git a/pkgs/development/compilers/ghdl/expected-output.txt b/pkgs/development/compilers/ghdl/expected-output.txt new file mode 100644 index 000000000000..0396b0c2787b --- /dev/null +++ b/pkgs/development/compilers/ghdl/expected-output.txt @@ -0,0 +1,8 @@ +simple-tb.vhd:71:5:@700ms:(report note): 32 +simple-tb.vhd:71:5:@900ms:(report note): 78 +simple-tb.vhd:71:5:@1100ms:(report note): 105 +simple-tb.vhd:71:5:@1300ms:(report note): 120 +simple-tb.vhd:71:5:@1500ms:(report note): 79 +simple-tb.vhd:71:5:@1700ms:(report note): 83 +simple-tb.vhd:71:5:@1900ms:(report note): 32 +simple-tb.vhd:75:1:@2100ms:(report note): All tests passed. diff --git a/pkgs/development/compilers/ghdl/simple-tb.vhd b/pkgs/development/compilers/ghdl/simple-tb.vhd new file mode 100644 index 000000000000..65e4d0967c52 --- /dev/null +++ b/pkgs/development/compilers/ghdl/simple-tb.vhd @@ -0,0 +1,78 @@ +library ieee; +use IEEE.STD_LOGIC_1164.all; +use ieee.numeric_std.all; + +library STD; +use STD.textio.all; + +entity tb is +end tb; + +architecture beh of tb is + +component simple +port ( + CLK, RESET : in std_ulogic; + DATA_OUT : out std_ulogic_vector(7 downto 0); + DONE_OUT : out std_ulogic +); +end component; + +signal data : std_ulogic_vector(7 downto 0) := "00100000"; +signal clk : std_ulogic; +signal RESET : std_ulogic := '0'; +signal done : std_ulogic := '0'; +signal cyclecount : integer := 0; + +constant cycle_time_c : time := 200 ms; +constant maxcycles : integer := 100; + +begin + +simple1 : simple +port map ( + CLK => clk, + RESET => RESET, + DATA_OUT => data, + DONE_OUT => done +); + +clk_process : process +begin + clk <= '0'; + wait for cycle_time_c/2; + clk <= '1'; + wait for cycle_time_c/2; +end process; + +count_process : process(CLK) +begin + if (CLK'event and CLK ='1') then + if (RESET = '1') then + cyclecount <= 0; + else + cyclecount <= cyclecount + 1; + end if; + end if; +end process; + +test : process + +begin + +RESET <= '1'; +wait until (clk'event and clk='1'); +wait until (clk'event and clk='1'); +RESET <= '0'; +wait until (clk'event and clk='1'); +for cyclecnt in 1 to maxcycles loop + exit when done = '1'; + wait until (clk'event and clk='1'); + report integer'image(to_integer(unsigned(data))); +end loop; +wait until (clk'event and clk='1'); + +report "All tests passed." severity NOTE; +wait; +end process; +end beh; diff --git a/pkgs/development/compilers/ghdl/simple.vhd b/pkgs/development/compilers/ghdl/simple.vhd new file mode 100644 index 000000000000..f10cf73d067c --- /dev/null +++ b/pkgs/development/compilers/ghdl/simple.vhd @@ -0,0 +1,45 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.ALL; +use IEEE.STD_LOGIC_MISC.or_reduce; + +entity simple is + +port ( + CLK, RESET : in std_ulogic; + DATA_OUT : out std_ulogic_vector(7 downto 0); + DONE_OUT : out std_ulogic +); +end simple; + +architecture beh of simple is + +signal data : std_ulogic_vector(7 downto 0); +signal done: std_ulogic; + +begin + +proc_ctr : process(CLK) +begin +if (CLK = '1' and CLK'event) then + if (RESET = '1') then + data <= "01011111"; + done <= '0'; + else + case data is + when "00100000" => data <= "01001110"; + when "01001110" => data <= "01101001"; + when "01101001" => data <= "01111000"; + when "01111000" => data <= "01001111"; + when "01001111" => data <= "01010011"; + when others => data <= "00100000"; + end case; + done <= not or_reduce(data xor "01010011"); + end if; +end if; +end process; + +DATA_OUT <= data; +DONE_OUT <= done; + +end beh; diff --git a/pkgs/development/compilers/ghdl/test-simple.nix b/pkgs/development/compilers/ghdl/test-simple.nix new file mode 100644 index 000000000000..8d3c3d3095f2 --- /dev/null +++ b/pkgs/development/compilers/ghdl/test-simple.nix @@ -0,0 +1,23 @@ +{ stdenv, ghdl-llvm, ghdl-mcode, backend }: + +let + ghdl = if backend == "llvm" then ghdl-llvm else ghdl-mcode; +in +stdenv.mkDerivation { + name = "ghdl-test-simple"; + meta.timeout = 300; + nativeBuildInputs = [ ghdl ]; + buildCommand = '' + cp ${./simple.vhd} simple.vhd + cp ${./simple-tb.vhd} simple-tb.vhd + mkdir -p ghdlwork + ghdl -a --workdir=ghdlwork --ieee=synopsys simple.vhd simple-tb.vhd + ghdl -e --workdir=ghdlwork --ieee=synopsys -o sim-simple tb + '' + (if backend == "llvm" then '' + ./sim-simple --assert-level=warning > output.txt + '' else '' + ghdl -r --workdir=ghdlwork --ieee=synopsys tb > output.txt + '') + '' + diff output.txt ${./expected-output.txt} && touch $out + ''; +}