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nixpkgs/pkgs/development/compilers/yosys/default.nix

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{ stdenv, fetchFromGitHub
, pkgconfig, bison, flex
, tcl, readline, libffi, python3
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, protobuf, zlib
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, verilog
}:
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with builtins;
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stdenv.mkDerivation rec {
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pname = "yosys";
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version = "2019.09.27";
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srcs = [
(fetchFromGitHub {
owner = "yosyshq";
repo = "yosys";
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rev = "c372e7baf9c48d41ebdbea4486a72e8dfaaddd3d";
sha256 = "18cyz900haf8lkpddqn0sns0a3hc8fqndzz7gg391671hzvy820k";
name = "yosys";
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})
# NOTE: the version of abc used here is synchronized with
# the one in the yosys Makefile of the version above;
# keep them the same for quality purposes.
(fetchFromGitHub {
owner = "berkeley-abc";
repo = "abc";
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rev = "5776ad07e7247993976bffed4802a5737c456782";
sha256 = "1la4idmssg44rp6hd63sd5vybvs3vr14yzvwcg03ls37p39cslnl";
name = "yosys-abc";
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})
];
sourceRoot = "yosys";
enableParallelBuilding = true;
nativeBuildInputs = [ pkgconfig ];
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buildInputs = [ tcl readline libffi python3 bison flex protobuf zlib ];
makeFlags = [ "ENABLE_PROTOBUF=1" ];
patchPhase = ''
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substituteInPlace ../yosys-abc/Makefile \
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--replace 'CC := gcc' "" \
--replace 'CXX := g++' ""
substituteInPlace ./Makefile \
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--replace 'CXX = clang' "" \
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--replace 'LD = clang++' 'LD = $(CXX)' \
--replace 'CXX = gcc' "" \
--replace 'LD = gcc' 'LD = $(CXX)' \
--replace 'ABCMKARGS = CC="$(CXX)" CXX="$(CXX)"' 'ABCMKARGS =' \
--replace 'echo UNKNOWN' 'echo ${substring 0 10 (elemAt srcs 0).rev}'
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patchShebangs tests
'';
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preBuild = ''
chmod -R u+w ../yosys-abc
ln -s ../yosys-abc abc
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make config-${if stdenv.cc.isClang or false then "clang" else "gcc"}
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echo 'ABCREV := default' >> Makefile.conf
makeFlags="PREFIX=$out $makeFlags"
# we have to do this ourselves for some reason...
(cd misc && ${protobuf}/bin/protoc --cpp_out ../backends/protobuf/ ./yosys.proto)
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'';
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doCheck = true;
checkInputs = [ verilog ];
# checkPhase defaults to VERBOSE=y, which gets passed down to abc,
# which then does $(VERBOSE)gcc, which then complains about not
# being able to find ygcc. Life is pain.
checkFlags = [ " " ];
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meta = {
description = "Framework for RTL synthesis tools";
longDescription = ''
Yosys is a framework for RTL synthesis tools. It currently has
extensive Verilog-2005 support and provides a basic set of
synthesis algorithms for various application domains.
Yosys can be adapted to perform any synthesis job by combining
the existing passes (algorithms) using synthesis scripts and
adding additional passes as needed by extending the yosys C++
code base.
'';
homepage = http://www.clifford.at/yosys/;
license = stdenv.lib.licenses.isc;
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maintainers = with stdenv.lib.maintainers; [ shell thoughtpolice emily ];
platforms = stdenv.lib.platforms.all;
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};
}