forked from mirrors/nixpkgs
79 lines
1.4 KiB
VHDL
79 lines
1.4 KiB
VHDL
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library ieee;
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use IEEE.STD_LOGIC_1164.all;
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use ieee.numeric_std.all;
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library STD;
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use STD.textio.all;
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entity tb is
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end tb;
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architecture beh of tb is
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component simple
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port (
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CLK, RESET : in std_ulogic;
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DATA_OUT : out std_ulogic_vector(7 downto 0);
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DONE_OUT : out std_ulogic
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);
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end component;
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signal data : std_ulogic_vector(7 downto 0) := "00100000";
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signal clk : std_ulogic;
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signal RESET : std_ulogic := '0';
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signal done : std_ulogic := '0';
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signal cyclecount : integer := 0;
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constant cycle_time_c : time := 200 ms;
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constant maxcycles : integer := 100;
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begin
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simple1 : simple
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port map (
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CLK => clk,
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RESET => RESET,
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DATA_OUT => data,
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DONE_OUT => done
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);
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clk_process : process
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begin
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clk <= '0';
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wait for cycle_time_c/2;
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clk <= '1';
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wait for cycle_time_c/2;
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end process;
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count_process : process(CLK)
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begin
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if (CLK'event and CLK ='1') then
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if (RESET = '1') then
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cyclecount <= 0;
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else
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cyclecount <= cyclecount + 1;
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end if;
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end if;
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end process;
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test : process
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begin
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RESET <= '1';
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wait until (clk'event and clk='1');
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wait until (clk'event and clk='1');
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RESET <= '0';
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wait until (clk'event and clk='1');
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for cyclecnt in 1 to maxcycles loop
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exit when done = '1';
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wait until (clk'event and clk='1');
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report integer'image(to_integer(unsigned(data)));
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end loop;
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wait until (clk'event and clk='1');
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report "All tests passed." severity NOTE;
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wait;
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end process;
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end beh;
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